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500 mhz to 1700 mhz balanced mixer, lo buffer, if amplifier, and rf balun ADL5357 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features rf frequency range of 500 mhz to 1700 mhz if frequency range of 30 mhz to 450 mhz power conversion gain: 8.6 db ssb noise figure of 9.1 db ssb noise figure with 5 dbm blocker of 19.5 db input ip3 of 26.6 dbm input p1db of 10.2 dbm typical lo drive of 0 dbm single-ended, 50 rf and lo input ports high isolation spdt lo input switch single-supply operation: 3.3 v to 5 v exposed paddle 5 mm 5 mm, 20-lead lfcsp 1500 v hbm/500 v ficdm esd performance applications cellular base station receivers transmit observation receivers radio link downconverters general description the ADL5357 uses a highly linear, doubly balanced passive mixer core along with integrated rf and lo balancing circuitry to allow for single-ended operation. the ADL5357 incorporates an rf balun, allowing for optimal performance over a 500 mhz to 1700 mhz rf input frequency range using high-side lo injection for rf frequencies from 500 mhz to 1200 mhz and low-side injection for frequencies from 900 mhz to 1700 mhz. the balanced passive mixer arrangement provides good lo-to-rf leakage, typically better than ?46 dbm, and excellent inter- modulation performance. the balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. a high linearity if buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8.6 db and can be used with a wide range of output impedances. functional block diagram 2 3 1 20 19 18 17 16 6 7 8 9 10 4 5 14 13 15 12 bias generator vpif rfin rfct comm comm loi2 vpsw vgs1 vgs0 loi1 ifgm ifop ifon pwdn lext vlo3 lgm3 vlo2 losw nc ADL5357 nc = no connect 11 0 8081-001 figure 1. the ADL5357 provides two switched lo paths that can be used in tdd applications where it is desirable to rapidly switch between two local oscillators. lo current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. for low voltage applications, the ADL5357 is capable of operation at voltages down to 3.3 v with substantially reduced current. under low voltage operation, an additional logic pin is provid ed to power down (<200 a) the circuit when desired. the ADL5357 is fabricated using a bicmos high performance ic process. the device is available in a 5 mm 5 mm, 20-lead lfcsp and operates over a ?40c to +85c temperature range. an evaluation board is also available. table 1. passive mixers rf frequency (mhz) single mixer single mixer + if amp dual mixer + if amp 500 to 1700 ADL5357 1200 to 2500 adl5355
ADL5357 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 5 v performance ........................................................................... 4 ? 3.3 v performance ........................................................................ 4 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? 5 v performance ........................................................................... 7 ? 3.3 v performance ...................................................................... 14 ? spur tables .................................................................................. 15 ? circuit description......................................................................... 16 ? rf subsystem .............................................................................. 16 ? lo subsystem ............................................................................. 17 ? applications information .............................................................. 18 ? basic connections ...................................................................... 18 ? if port .......................................................................................... 18 ? bias resistor selection ............................................................... 18 ? mixer vgs control dac .......................................................... 18 ? evaluation board ............................................................................ 20 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 23 ? revision history 7/09revision 0: initial version
ADL5357 rev. 0 | page 3 of 24 specifications v pos = 5 v, i s = 190 ma, t a = 25c, f rf = 900 mhz, f lo = 1103 mhz, lo power = 0 dbm, z o = 50 , unless otherwise noted. table 2. parameter conditions min typ max unit rf input interface return loss tunable to >20 db over a limited bandwidth 19 db input impedance 50 rf frequency range 500 1700 mhz output interface output impedance differential impedance, f = 200 mhz 240||0.4 ||pf if frequency range 30 450 mhz dc bias voltage 1 externally generated 3.3 5.0 5.5 v lo interface lo power ?6 0 +10 dbm return loss 12 db input impedance 50 lo frequency range 730 1670 mhz power-down (pwdn) interface 2 pwdn threshold 1.0 v logic 0 level 0.4 v logic 1 level 1.4 v pwdn response time device enabled, if output to 90% of its final level 160 ns device disabled, supply current < 5 ma 220 ns pwdn input bias current device enabled 0.0 a device disabled 70 a 1 apply the supply voltage from the external circuit through the choke inductors. 2 the pwdn function is intended for use with v pos 3.6 v only.
ADL5357 rev. 0 | page 4 of 24 5 v performance v pos = 5 v, i s = 190 ma, t a = 25c, f rf = 900 mhz, f lo = 1103 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. table 3. parameter conditions min typ max unit dynamic performance power conversion gain including 4:1 if port transformer and pcb loss 7 8.6 9.5 db voltage conversion gain z source = 50 , differential z load = 200 differential 14.9 db ssb noise figure 9.1 db ssb noise figure under blocking 5 dbm blocker present 10 mhz from wanted rf input, lo source filtered 19.5 db input third-order intercept (iip3) f rf1 = 899.5 mhz, f rf2 = 900.5 mhz, f lo = 1103 mhz, each rf tone at ?10 dbm 22 26.6 dbm input second-order intercept (iip2) f rf1 = 950 mhz, f rf2 = 900 mhz, f lo = 1103 mhz, each rf tone at ?10 dbm 62.8 dbm input 1 db compression point (ip1db) 10.2 dbm lo-to-if leakage unfiltered if output ?7 dbm lo-to-rf leakage ?46.7 dbm rf-to-if isolation ?35 dbc if/2 spurious ?10 dbm input power ?69.2 dbc if/3 spurious ?10 dbm input power ?83.4 dbc power supply positive supply voltage 4.5 5 5.5 v quiescent current lo supply, resistor programmable 100 ma if supply, resistor programmable 90 ma total quiescent current v pos = 5 v 190 ma 3.3 v performance v pos = 3.3 v, i s = 125 ma, t a = 25c, f rf = 900 mhz, f lo = 1103 mhz, lo power = 0 dbm, r9 = 226 , r14 = 604 , vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. table 4. parameter conditions min typ max unit dynamic performance power conversion gain including 4:1 if port transformer and pcb loss 8.8 db voltage conversion gain z source = 50 , differential z load = 200 differential 15.1 db ssb noise figure 9.0 db input third-order intercept (iip3) f rf1 = 899.5 mhz, f rf2 = 900.5 mhz, f lo = 1103 mhz, each rf tone at ?10 dbm 21.4 dbm input second-order intercept (iip2) f rf1 = 950 mhz, f rf2 = 900 mhz, f lo = 1103 mhz, each rf tone at ?10 dbm 55.7 dbm input 1 db compression point (ip1db) 7.1 dbm power interface supply voltage 3.0 3.3 3.6 v quiescent current resistor programmable 125 ma power-down current device disabled 150 a
ADL5357 rev. 0 | page 5 of 24 absolute maximum ratings table 5. parameter rating supply voltage, v pos 5.5 v rf input level 20 dbm lo input level 13 dbm ifop, ifon bias voltage 6.0 v vgs0, vgs1, losw, pwdn 5.5 v internal power dissipation 1.2 w ja 25c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature range (soldering, 60 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADL5357 rev. 0 | page 6 of 24 pin configuration and fu nction descriptions pin 1 indicator notes 1. 2 nc = no connect. . exposed pad. must be soldered to ground. 1 vpif 2 rfin 3 rfct 4 comm 5 comm 13 vgs1 14 vpsw 15 loi2 12 vgs0 11 loi1 6 v l o 3 7 l g m 3 8 v l o 2 1 0 n c 9 l o s w 1 8 i f o n 1 9 i f o p 2 0 i f g m 1 7 p w d n 1 6 l e x t top view (not to scale) ADL5357 08081-002 figure 2. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 vpif positive supply voltage for if amplifier. 2 rfin rf input. must be ac-coupled. 3 rfct rf balun center tap (ac ground). 4, 5 comm device common (dc ground). 6, 8 vlo3, vlo2 positive supply voltages for lo amplifier. 7 lgm3 lo amplifier bias control. 9 losw lo switch. loi1 selected for 0 v, and loi2 selected for 3 v. 10 nc no connect. 11, 15 loi1, loi2 lo inputs. must be ac-coupled. 12, 13 vgs0, vgs1 mixer gate bias controls. 3 v logic. ground these pins for nominal setting. 14 vpsw positive supply voltage for lo switch. 16 lext if return. this pin must be grounded. 17 pwdn power down. connect this pin to ground for normal operation and connect this pin to 3.0 v for disable mode. 18, 19 ifon, ifop differential if outputs (open co llectors). each requires an external dc bias. 20 ifgm if amplifier bias control. epad (ep) exposed pad. must be soldered to ground.
ADL5357 rev. 0 | page 7 of 24 typical performance characteristics 5 v performance v pos = 5 v, i s = 190 ma, t a = 25c, f rf = 900 mhz, f lo = 1103 mhz, lo power = 0 dbm, r9 = 1.1 k, r14 = 910 , vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 150 160 170 180 190 200 210 220 700 750 800 850 900 950 1000 1050 1100 1150 1200 supply current (ma) rf frequency (mhz) 08081-034 t a = +25c t a = +85c t a = ?40c figure 3. supply current vs. rf frequency 0 2 4 6 8 10 12 700 750 800 850 900 950 1000 1050 1100 1150 1200 conversion gain (db) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c 08081-015 figure 4. power conversion gain vs. rf frequency 0 5 10 15 20 25 30 35 700 750 800 850 900 950 1000 1050 1100 1150 1200 input ip3 (dbm) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c 08081-021 figure 5. input ip3 vs. rf frequency 0 10 20 30 40 50 60 70 80 700 750 800 850 900 950 1000 1050 1100 1150 1200 input ip2 (dbm) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c 0 8081-019 figure 6. input ip2 vs. rf frequency 6 7 8 9 10 11 12 13 14 700 750 800 850 900 950 1000 1050 1100 1150 1200 input p1db (dbm) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c 08081-024 figure 7. input p1db vs. rf frequency 0 2 4 6 8 10 12 14 16 18 20 700 750 800 850 900 950 1000 1050 1100 1150 1200 ssb noise figure (db) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c 08081-027 figure 8. ssb noise figu re vs. rf frequency
ADL5357 rev. 0 | page 8 of 24 0 50 100 150 200 250 ?40 ?20 0 20 40 60 80 supply current (ma) temperature (c) v pos = 4.75v v pos = 5v v pos = 5.25v 08081-035 figure 9. supply current vs. temperature 08081-046 4 5 6 7 8 9 10 ?40 ?20 0 20 40 60 80 conversion gain (db) temperature (c) v pos = 4.75v v pos = 5.0v v pos = 5.25v figure 10. power conversion gain vs. temperature 08081-048 ?40 ?20 0 20 40 60 80 temperature (c) 15 17 19 21 23 25 27 29 31 33 35 input ip3 (dbm) v pos = 5.25v v pos = 4.75v v pos = 5.0v figure 11. input ip3 vs. temperature 08081-047 ?40 ?20 0 20 40 60 80 0 10 20 30 40 50 60 70 80 input ip2 (dbm) temperature (c) v pos = 5.25v v pos = 4.75v v pos = 5.0v figure 12. input ip2 vs. temperature 08081-049 4 5 6 7 8 9 10 11 12 13 14 input p1db (dbm) ?40 ?20 0 20 40 60 80 temperature (c) v pos = 5.25v v pos = 4.75v v pos = 5.0v figure 13. input p1db vs. temperature 6 7 8 9 10 11 12 ?40 ?20 0 20 40 60 80 ssb noise figure (db) temperature (c) v pos = 5.25v v pos = 4.75v v pos = 5.0v 0 8081-028 figure 14. ssb noise figure vs. temperature
ADL5357 rev. 0 | page 9 of 24 150 160 170 180 190 200 210 220 30 80 130 180 230 280 330 380 430 supply current (ma) if frequency (mhz) t a = +85c t a = ?40c t a = +25c 08081-031 figure 15. supply current vs. if frequency 0 2 4 6 8 10 12 30 80 130 180 230 280 330 380 430 conversion gain (db) if frequency (mhz) 0 2 4 6 8 10 12 t a = +25c t a = +85c t a = ?40c 08081-013 figure 16. power conversion gain vs. if frequency 0 5 10 15 20 25 30 35 30 80 130 180 230 280 330 380 430 input ip3 (dbm) if frequency (mhz) t a = +25c t a = +85c t a = ?40c 08081-020 figure 17. input ip3 vs. if frequency 0 10 20 30 40 50 60 70 80 30 80 130 180 230 280 330 380 430 input ip2 (dbm) if frequency (mhz) t a = +25c t a = +85c t a = ?40c 08081-017 figure 18. input ip2 vs. if frequency 0 2 4 6 8 10 12 30 80 130 180 230 280 330 380 430 input p1db (dbm) if frequency (mhz) t a = +25c t a = +85c t a = ?40c 08081-022 figure 19. input p1db vs. if frequency 5 6 7 8 9 10 11 12 13 14 15 30 80 130 180 230 280 330 380 430 ssb noise figure (db) if frequency (mhz) 08081-011 figure 20. ssb noise figure vs. if frequency
ADL5357 rev. 0 | page 10 of 24 ?6 ?4 ?2 0 2 4 6 8 10 conversion gain (db) lo power level (dbm) 0 2 4 6 8 10 12 t a = +25c t a = +85c t a = ?40c 08081-014 figure 21. power conversion gain vs. lo power 0 5 10 15 20 25 30 6420246810 input ip3 (dbm) lo power level (dbm) t a = +25c t a = +85c t a = ?40c 0 8081-016 figure 22. input ip3 vs. lo power 0 10 20 30 40 50 60 70 80 ?6 ?4 ?2 0 2 4 6 8 10 input ip2 (dbm) lo power (dbm) t a = +25c t a = +85c t a = ?40c 08081-018 figure 23. input ip2 vs. lo power 08081-023 0 2 4 6 8 10 12 ?6 ?4 ?2 0 2 4 6 8 10 input p1db (dbm) lo power (dbm) t a = +25c t a = +85c t a = ?40c figure 24. input p1db vs. lo power ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 700 750 800 850 900 950 1000 1050 1100 1150 1200 if/2 spurious (dbc) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c 08081-007 figure 25. if/2 spurio us vs. rf frequency ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 700 750 800 850 900 950 1000 1050 1100 1150 1200 if/3 spurious (dbc) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c 0 8081-008 figure 26. if/3 spurio us vs. rf frequency
ADL5357 rev. 0 | page 11 of 24 08081-044 100 80 60 40 20 8.38.48.58.68.78.88.9 0 distribution percentage (%) conversion gain (db) mean: 8.59 sd: 0.14% figure 27. power conversion gain distribution 08081-043 100 80 60 40 20 24 25 26 27 28 29 0 distribution percentage (%) input ip3 (dbm) mean: 26.57 sd: 0.39% figure 28. input ip3 distribution 08081-045 input p1db (dbm) 100 80 60 40 20 0 distribution percentage (%) mean: 10.22 sd: 0.50% 9.6 9.9 10.2 10.5 10.8 figure 29. input p1db distribution 08081-050 0 100 200 300 400 500 resistance ( ? ) capacitance (pf) 30 80 130 280 230 180 330 380 430 0 2 4 6 8 10 if frequency (mhz) figure 30. if port return loss 40 35 30 25 20 15 10 5 0 700 750 800 850 900 950 1000 1050 1100 1150 1200 rf return loss (db) rf frequency (mhz) 08081-029 figure 31. rf port return loss, fixed if 30 25 20 15 10 5 0 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 lo return loss (db) lo frequency (mhz) selected unselected 08081-038 figure 32. lo return loss, selected and unselected
ADL5357 rev. 0 | page 12 of 24 08081-041 40 45 50 55 60 65 70 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 lo switch isol a tion (db) lo frequency (mhz) t a = ?40c t a = +85c t a = +25c figure 33. lo switch isolation vs. lo frequency ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 700 750 800 850 900 950 1000 1050 1100 1150 1200 rf-to-if isol a tion (dbc) rf frequency (mhz) t a = +85c t a = ?40c t a = +25c 08081-030 figure 34. rf-to-if isolation vs. rf frequency ?30 ?25 ?20 ?15 ?10 ?5 0 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 lo-to-if leakage (dbm) lo frequency (mhz) t a = +25c t a = +85c t a = ?40c 08081-025 figure 35. lo-to-if leakage vs. lo frequency ?60 ?50 ?40 ?30 ?20 ?10 0 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 lo-to-rf leakage (dbm) lo frequency (mhz) t a = +85c t a = ?40c t a = +25c 0 8081-026 figure 36. lo-to-rf leakage vs. lo frequency 08081-039 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 2lo leakage (dbm) lo frequency (mhz) 2lo to if 2lo to rf figure 37. 2lo leakag e vs. lo frequency 08081-040 ?60 ?50 ?40 ?30 ?20 ?10 0 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 3lo leakage (dbm) lo frequency (mhz) 3lo to rf 3lo to if figure 38. 3lo leakag e vs. lo frequency
ADL5357 rev. 0 | page 13 of 24 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 700 750 800 850 900 950 1000 1050 1100 1150 1200 ssb noise figure (db) conversion gain (db) rf frequency (mhz) vgs = 00 vgs = 01 vgs = 10 vgs = 11 08081-037 ssb noise figure conversion gain figure 39. power conversion gain and ssb noise figure vs. rf frequency 16 18 20 22 24 26 28 30 6 8 10 12 14 16 18 20 700 750 800 850 900 950 1000 1050 1100 1150 1200 input ip3 (dbm) input p1db (dbm) rf frequency (mhz) vgs = 00 vgs = 01 vgs = 10 vgs = 11 08081-036 input ip3 input p1db figure 40. input p1db and input ip3 vs. rf frequency 0 5 10 15 20 25 30 6 7 8 9 10 11 12 input ip3 (dbm) conversion gain and ssb noise figure (db) lo bias resistor value (k ? ) 08081-012 conversion gain ssb noise figure input ip3 0.60.81.01.21.41.61.8 figure 41. power conversion gain, ssb noise figure, and input ip3 vs. lo bias resistor value 08081-042 0 5 10 15 20 25 30 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 noise figure (db) blocker power (dbm) figure 42. ssb noise figure vs.10 mhz offset blocker level 0 20 40 60 80 100 120 140 600 800 1000 1200 1400 1600 1800 supply current (ma) bias resistor value ( ? ) 08081-033 r9 lo set resistor r14 if set resistor figure 43. if or lo supply current vs. if or lo bias resistor value 08081-059 0 5 10 15 20 25 30 6 7 8 9 10 11 12 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 input ip3 (dbm) conversion gain and ssb noise figure (db) if bias resistor value (k ? ) conversion gain ssb noise figure input ip3 figure 44. power conversion gain, ssb noise figure, and input ip3 vs. if bias resistor value
ADL5357 rev. 0 | page 14 of 24 3.3 v performance v pos = 3.3 v, i s = 125 ma, t a = 25c, f rf = 900 mhz, f lo = 1103 mhz, lo power = 0 dbm, r9 = 226 , r14 = 604 , vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. 08081-064 700 750 800 850 900 950 1000 1050 1100 1150 1200 supply current (ma) rf frequency (mhz) 60 70 80 90 100 110 120 130 140 150 160 t a = +85c t a = ?40c t a = +25c figure 45. supply current vs. rf frequency at 3.3 v 08081-060 0 2 4 6 8 10 12 700 750 800 850 900 950 1000 1050 1100 1150 1200 conversion gain (db) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c figure 46. power conversion gain vs. rf frequency at 3.3 v 08081-062 0 5 10 15 20 25 700 750 800 850 900 950 1000 1050 1100 1150 1200 input ip3 (dbm) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c figure 47. input ip3 vs. rf frequency at 3.3 v 08081-061 0 10 20 30 40 50 60 70 80 700 750 800 850 900 950 1000 1050 1100 1150 1200 input ip2 (dbm) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c figure 48. input ip2 vs. rf frequency at 3.3 v 08081-063 0 2 4 6 8 10 12 700 750 800 850 900 950 1000 1050 1100 1150 1200 input p1db (dbm) rf frequency (mhz) t a = +25c t a = +85c t a = ?40c figure 49. input p1db vs. rf frequency at 3.3 v ssb noise figure (db) rf frequency (mhz) 08081-051 2 4 6 8 10 12 14 700 750 800 850 900 950 1000 1050 1100 1150 1200 t a = +25c t a = +85c t a = ?40c figure 50. ssb noise figure vs. rf frequency at 3.3 v
ADL5357 rev. 0 | page 15 of 24 spur tables all spur tables are (n f rf ) ? (m f lo ) and were measured using the standard evaluation board. mixer spurious products are measured in dbc from the if output power level. data was only measured fo r frequencies less than 6 ghz. typical noise floor of the measu rement system = ?100 dbm. 5 v performance v pos = 5 v, i s = 190 ma, t a = 25c, f rf = 900 mhz, f lo = 1103 mhz, lo power = 0 dbm, vgs0 = vgs1 = 0 v, and z o = 50 , unless otherwise noted. table 7. m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n 0 ?4.8 ?15.8 ?33.5 ?38.6 ?55.7 1 ?41.3 0.0 ?47.1 ?37.9 ?57.9 ?57.3 ?74.9 2 ?87.1 ?65.5 ?73.4 ?78.8 ?87.3 ?93.1 ?92.1 ADL5357 rev. 0 | page 16 of 24 circuit description rf subsystem the ADL5357 consists of two primary components: the radio frequency (rf) subsystem and the local oscillator (lo) subsystem. the combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. in addition, the need for external components is minimized, optimizing cost and size. the single-ended, 50 rf input is internally transformed to a balanced signal using a low loss (<1 db) unbalanced-to-balanced (balun) transformer. this transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the rf port. although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. the rf balun can easily support an rf input frequency range of 500 mhz to 1700 mhz. the rf subsystem consists of an integrated, low loss rf balun, passive mosfet mixer, sum termination network, and if amplifier. the resulting balanced rf signal is applied to a passive mixer that commutates the rf input with the output of the lo subsystem. the passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. the only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. the lo subsystem consists of an spdt-terminated fet switch and a three-stage limiting lo amplifier. the purpose of the lo subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the lo input. a block diagram of the device is shown in figure 51 . because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (m n product) frequencies generated by the mixing process. terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the if amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. this termination is accomplished by the addition of a sum network between the if amplifier and the mixer and also in the feedback elements in the if amplifier. 2 3 1 20 19 18 17 16 6 7 8 9 10 4 5 14 13 15 12 bias generator vpif rfin rfct comm comm loi2 vpsw vgs1 vgs0 loi1 ifgm ifop ifon pwdn lext vlo3 lgm3 vlo2 losw nc ADL5357 nc = no connect 11 0 8081-001 the if amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that are required to achieve the overall performance. the balanced open- collector output of the if amplifier, with impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or an analog-to-digital input while providing optimum second- order intermodulation suppression. the differential output impedance of the if amplifier is approximately 200 . if operation in a 50 system is desired, the output can be transformed to 50 by using a 4:1 transformer. figure 51. simplified schematic the intermodulation performance of the design is generally limited by the if amplifier. the ip3 performance can be optimized by adjusting the if current with an external resistor. figure 41 , figure 43 , and figure 44 illustrate how various if and lo bias resistors affect the performance with a 5 v supply. additionally, dc current can be saved by increasing either or both resistors. it is permissible to reduce the dc supply voltage to as low as 3.3 v, further reducing the dissipated power of the part. (note that no performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.)
ADL5357 rev. 0 | page 17 of 24 lo subsystem the lo amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation performance. the resulting amplifier provides extremely high performance centered on an operating frequency of 1100 mhz. the best operation is achieved with either high-side lo injection for rf signals in the 500 mhz to 1200 mhz range or high-side injection for rf signals in the 900 mhz to 1700 mhz range. operation outside these ranges is permissible, and conversion gain is extremely wideband, easily spanning 500 mhz to 1700 mhz, but intermodulation is optimal over the aforementioned ranges. the ADL5357 has two lo inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. the two inputs are applied to a high isolation spdt switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the lo sources. this multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted lo input that may result in undesired if responses. the single-ended lo input is converted to a fixed amplitude differential signal using a multistage, limiting lo amplifier. this results in consistent performance over a range of lo input power. optimum performance is achieved from ?6 dbm to +10 dbm, but the circuit continues to function at considerably lower levels of lo input power. the performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. this is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. the bandwidth of the intermodulation performance is somewhat influenced by the current in the lo amplifier chain. for dc current sensitive applications, it is permissible to reduce the current in the lo amplifier by raising the value of the external bias control resistor. for dc current critical applications, the lo chain can operate with a supply voltage as low as 3.3 v, resulting in substantial dc power savings. in addition, when operating with supply voltages below 3.6 v, the ADL5357 has a power-down mode that permits the dc current to drop to <200 a. all of the logic inputs are designed to work with any logic family that provides a logic 0 input level of less than 0.4 v and a logic 1 input level that exceeds 1.4 v. all logic inputs are high impedance up to logic 1 levels of 3.3 v. at levels exceeding 3.3 v, protection circuitry permits operation up to 5.5 v, although a small bias current is drawn. all pins, including the rf pins, are esd protected and have been tested up to a level of 1500 v hbm and 500 v cdm.
ADL5357 rev. 0 | page 18 of 24 applications information basic connections the ADL5357 mixer is designed to downconvert radio frequencies (rf) primarily between 500 mhz and 1700 mhz to lower intermediate frequencies (if) between 30 mhz and 450 mhz. figure 52 depicts the basic connections of the mixer. it is recommended to ac couple rf and lo input ports to prevent non-zero dc voltages from damaging the rf balun or lo input circuit. the rfin capacitor value of 8 pf is recommended to provide the optimized rf input return loss for the desired frequency band. if port the mixer differential if interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. the shunting impedance of the choke inductors used to couple dc current into the if amplifier should be selected to provide the desired output return loss. the real part of the output impedance is approximately 200 , as seen in figure 30 , which matches many commonly used saw filters without the need for a transformer. this results in a voltage conversion gain that is approximately 6 db higher than the power conversion gain, as shown in table 3 . when a 50 output impedance is needed, use a 4:1 impedance transformer, as shown in figure 52 . bias resistor selection two external resistors, r bias if and r bias lo , are used to adjust the bias current of the integrated amplifiers at the if and lo terminals. it is necessary to have a sufficient amount of current to bias both the internal if and lo amplifiers to optimize dc current vs. optimum iip3 performance. figure 41 , figure 43 , and figure 44 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and ip3 performance. mixer vgs control dac the ADL5357 features two logic control pins, vgs0 (pin 12) and vgs1 (pin 13), that allow programmability for internal gate-to- source voltages for optimizing mixer performance over desired frequency bands. the evaluation board defaults both vgs0 and vgs1 to ground. power conversion gain, iip3, nf, and ip1db can be optimized, as is shown in figure 39 and figure 40 .
ADL5357 rev. 0 | page 19 of 24 2 3 1 19 18 17 16 6 7 8 9 10 14 15 12 11 bias generator lo2 in rf in +5v +5v +5v +5v lo1 in 470nh 470nh if out +5 v 100pf 10k ? 10k ? 10pf 10pf 10pf 8pf 10pf 0.1f 4.7f r bias lo r bias if 150pf 4:1 22pf 10pf 22pf ADL5357 20 13 5 4 08081-005 figure 52. typical application circuit
ADL5357 rev. 0 | page 20 of 24 evaluation board an evaluation board is available for the family of double balanced mixers. the standard evaluation board schematic is shown in figure 53 . the evaluation board is fabricated using rogers? ro3003 material. table 9 describes the various configuration options of the evaluation board. evaluation board layout is shown in figure 54 to figure 57 . 0 8081-006 c22 1nf c20 10pf c2 10f c21 10pf c1 8pf c10 22nf c12 22pf vgs1 lo2_in lo1_in rf-in r22 10k ? vpos pwr_up vpos if1-out r23 15k ? vpos vpos vpos losel vgs0 c5 0.01f c4 10pf c19 100pf c18 100pf c17 150pf r24 0 ? r25 0 ? l4 470nh l5 470nh c6 10pf c8 10pf r9 1.1k ? r4 10k ? r21 10k ? r1 0 ? r14 910 ? l3 0 ? t1 vpif rfin rfct comm comm vgs1 vpsw loi2 vgs0 loi1 i f o n i f o p i f g m p w d n l e x t v l o 3 l g m 3 v l o 2 n c l o s w ADL5357 figure 53. evaluation board schematic
ADL5357 rev. 0 | page 21 of 24 table 9. evaluation board configuration components description default conditions c2, c6, c8, c18, c19, c20, c21 power supply decoupling. nominal supply decoupling consists of a 10 f capacitor to ground in parallel with a 10 pf capacitor to ground positioned as close to the device as possible. c2 = 10 f (size 0603), c6, c8, c20, c21 = 10 pf (size 0402), c18, c19 = 100 pf (size 0402) c1, c4, c5 rf input interface. the input channels are ac-coupled through c1. c4 and c5 provide bypassing for the center taps of the rf input baluns. c1 = 8 pf (size 0402), c4 = 10 pf (size 0402), c5 = 0.01 f (size 0402) t1, c17, l4, l5, r1, r24, r25 if output interface. the open-collector if output interfaces are biased through pull-up choke inductors l4 and l5. t1 is a 4:1 impedance transformer used to provide a single-ended if output interface, with c17 providing center-tap bypassing. remove r1 for balanced output operation. t1 = tc4-1w+ (mini-circuits), c17 = 150 pf (size 0402), l4, l5 = 470 nh (size 1008), r1, r24, r25 = 0 (size 0402) c10, c12, r4 lo interface. c10 and c12 provide ac coupling for the lo1_in and lo2_in local oscillator inputs. losel selects the appropriate lo input for both mixer cores. r4 provides a pull-down to ensure that lo1_in is enabled when the losel test point is logic low. lo2_in is enabled when los el is pulled to logic high. c10, c12 = 22 pf (size 0402), r4 = 10 k (size 0402) r21 pwdn interface. r21 pulls the pwdn logic low and enables the device. the pwr_up test point al lows the pwdn interface to be exercised using the external logic generator. grounding the pwdn pin for nominal operation is allowed. using the pwdn pin when supply voltages exceed 3.3 v is not allowed. r21 = 10 k (size 0402) c22, l3, r9, r14, r22, r23, vgs0, vgs1 bias control. r22 and r23 form a voltage divider to provide 3 v for logic control, bypassed to ground through c22. vgs0 and vgs1 jumpers provide programmability at the vgs0 and vgs1 pins. it is recommended to pull these two pins to ground for nominal operation. r9 sets the bias point for the internal lo buffers. r14 sets the bias point for the internal if amplifier. c22 = 1 nf (size 0402), l3 = 0 (size 0603), r9 = 1.1 k (size 0402), r14 = 910 (size 0402), r22 = 10 k (size 0402), r23 = 15 k (size 0402), vgs0 = vgs1 = 3-pin shunt
ADL5357 rev. 0 | page 22 of 24 08081-055 figure 54. evaluation board top layer 08081-056 figure 55. evaluation board ground plane, internal layer 1 08081-057 figure 56. evaluation board power plane, internal layer 2 08081-058 figure 57. evaluation board bottom layer
ADL5357 rev. 0 | page 23 of 24 outline dimensions compliant to jedec standards mo-220-vhhc 042209-b 1 0.65 bsc p i n 1 i n d i c a t o r 2.60 bsc 0.75 0.60 0.50 top view 12 max seating plane pin 1 indi c ator coplanarity 0.05 0.90 0.85 0.80 0.35 0.28 0.23 0.05 max 0.01 nom 0.20 ref 0.70 0.65 0.60 3.20 3.10 sq 3.00 20 6 16 10 11 15 5 exposed pad (bottom view) 0.60 max 0.60 max 5.00 bsc sq 4.75 bsc sq for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 58. 20-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-20-5) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity ADL5357acpz-r7 1 ?40c to +85c 20-lead lead frame chip scale pa ckage [lfcsp_vq] cp-20-5 1,500, 7 tape and reel ADL5357acpz-wp 1 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-5 36, waffle pack ADL5357-evalz 1 evaluation board 1 1 z = rohs compliant part.
ADL5357 rev. 0 | page 24 of 24 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08081-0-7/09(0)

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